This application claims benefit of priority under 35 U.S.C. xc2xa7 119 to Japanese Patent Applications No. H11-129321, filed on May 10, 1999, and 2000-65397, filed on Mar. 9, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a semiconductor device, such as an electrically rewritable nonvolatile semiconductor memory device (EEPROM flash memory). More specifically, the invention relates to a flash memory system capable of simultaneously executing a data write or erase operation and a data read operation.
2. Description of the Related Background Art
Conventionally, there are various electronic systems wherein a plurality of memory devices are incorporated. For example, there is an electronic system wherein an EEPROM flash memory and an SRAM are incorporated to store data of the flash memory in the SRAM to exchange data between a CPU and the flash memory via the SRAM and to be capable of directly rewriting data of the flash memory without passing through the SRAM.
On the other hand, there is recently known a memory system called a read while write (RWW) type memory system capable of reading data out from a certain memory region while writing or erasing data in another memory region in order to reduce the number of memory chips necessary for the system. In order to form a memory device of this type, completely independent two memory regions may be simply provided in the memory device.
However, if the independently accessed regions are only simply provided in the memory device, there are problems as an RWW type memory system. First, since each of the memory regions independently requires a decoder and a sense amplifier, the layout area thereof is large. Secondly, if bit lines and word lines are continuously arranged independently every one of the memory regions, it is not possible to divide each of the memory regions into blocks to read and write data every block. That is, the range of the parallel execution of a data read operation and a data write operation is fixed, so that the system can not be applied to many uses. In order for the system to be applied many uses, a plurality of kinds of systems having different capacities of memory regions must be prepared.
In a conventional flash memory capable of simultaneously executing a data write or erase operation and a data read operation, a memory cell array is physically fixed to two banks. For example, considering a 32-Mbit flash memory chip, the capacity thereof is fixed so that one of the banks has 0.5 Mbits and the other bank has 31.5 Mbits. Therefore, users must newly buy another chip when requiring a different bank size.
In addition, as a circuit construction, dedicated address and data lines are provided every bank. When a write or erase operation is executed in blocks of one of banks, the power supply line of the one of the banks is connected to a writing or erasing power supply line by a power supply switch, and the power supply line of the other bank is connected to a reading power supply side. If the opposite operation instruction is inputted, each of the banks is connected to the power supply line on the opposite side by a corresponding one of the power supply switches.
Moreover, a set of sense amplifiers for detecting memory cell data are provided exclusively for each of the banks. For that reason, although it is possible to execute a read operation from memory cells in one of the banks while executing a write or erase in blocks in the other bank, it is impossible to simultaneously execute a write or erase operation and a read operation in the same bank.
In addition, since the banks are physically fixed, there is a severe limit to addresses capable of being simultaneously executed, and the size of each of the banks is also fixed, so that the degree of freedom is very low.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a nonvolatile semiconductor memory device having a plurality of cores which are a set of blocks serving as a unit of data erase, and capable of simultaneously executing a data write or erase operation in an optional core and a data read operation in another optional core.
It is another object of the present invention to provide a nonvolatile semiconductor memory device capable of setting the size of each of banks, each of which is a range of optionally selected cores, and of simultaneously executing a data write or erase operation and a data read operation in two banks.
It is a further object of the present invention to a semiconductor device having a chip size which can be decreased by efficiently arranging a common bus line with respect to a plurality of functional blocks.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor device comprises: a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of the memory cells being an electrically rewritable nonvolatile memory cell; core selecting portion configured to select an optional number of cores from the plurality of cores for writing or erasing data; data writing portion configured to write data in a selected memory cell in a core selected by the core selecting portion; data erasing portion to erase data from a selected block in a core selected by the core selecting portion; and data reading portion configured to read data out from a memory cell in a core which is not selected by the core selecting portion.
According to the present invention, it is possible to obtain a flash memory of a free core system capable of selecting an optional core from a plurality of cores, each of which comprises one block or a set of a plurality of blocks, to write or erase data in the selected core while reading data out from another optional core.
According to another aspect of the present invention, a semiconductor device comprises: a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of the memory cells being an electrically rewritable nonvolatile memory cell; a bank setting memory circuit for selecting an optional number of cores of the plurality of cores as a first bank and for setting the remaining cores as a second bank; core selecting portion configured to select an optional number of cores from the plurality of cores for writing or erasing data in each of the first and second banks; bank busy output circuits for outputting a bank busy output indicating that one of the first and second banks is in a data write or erase mode, on the basis of the core selecting portion and data stored in the bank setting memory circuit; data writing portion configured to write data in a selected memory cell of one of the first and second banks; data erasing portion configured to erase data from a selected block of one of the first and second banks; and data reading portion configured to read data out from one of the first and second banks, which is not in the data write or erase mode.
According to the present invention, it is possible to obtain a flash memory of a free bank system capable of optionally setting a bank size by causing a bank setting memory circuit to set optionally selected cores as a first bank and to set the remaining cores as a second bank, so that it is possible to read data in the second bank while writing or erasing data in optional blocks in the first bank.
Throughout the specification, the term xe2x80x9ccorexe2x80x9d means a set of blocks serving as a unit of data erase as described above. Specifically, the xe2x80x9ccorexe2x80x9d means a lump of a plurality of blocks sharing address lines, power supply lines and data lines, and a set of a plurality of blocks, to one block of which access is inhibited while access to another block is given.
Specifically, in order to realize a free core system according to the present invention, the semiconductor device further may comprise: a first data bus line which is provided commonly for the plurality of cores and which is used during a data read operation; a first sense amplifier circuit which is connected to the first data bus line and which is used during the data read operation; a second data bus line which is provided commonly for the plurality of cores and which is used during a data write or erase operation; and a second sense amplifier circuit which is connected to the second data bus line and which is used for carrying out a verify read operation during the data write or erase operation.
More preferably, the first data bus line, which is provided commonly for the plurality of cores and which is used during the data read operation, and the second data bus line, which is provided commonly for the plurality of cores and which is used during the data write or erase operation, are separately prepared.
In addition, in order to realize a free core system according to the present invention, each of the cores may comprise: a decoder circuit for allowing simultaneous execution of a data write or erase operation in an optional core of the plurality of cores and a data read operation in other cores of the plurality of cores; an address line switching circuit for selectively supplying one of an address signal of the first address bus line and an address signal of the second address bus line to the decoder circuit, in accordance with whether a corresponding one of the plurality of cores is in a data read mode or a data write or erase mode; and a data line switching circuit for selectively connecting one of the first data bus line and the second data bus line to a data line of a corresponding one of the plurality of cores, in accordance with whether the corresponding one of the plurality of cores is in the data read mode or the data write or erase mode.
More specifically, a first power supply line, which is provided commonly for the plurality of cores and which is used during a data read operation, and a second power supply line, which is provided commonly for the plurality of cores and which is used during a data write or erase operation, may be separately prepared, and each of the cores may be provided with a power supply line switching circuit for selectively supplying one of a data reading power supply potential of the first power supply line and a data writing or erasing power supply potential of the second power supply line to the decoder circuit, in accordance with whether the corresponding one of the cores is in a data read mode or a data write or erase mode.
In addition, according to the present invention, an address buffer may be designed to supply an inputted address signal to the first address bus line without latching the inputted address signal during a data read operation, to latch and supply an inputted address signal to the second address bus line during a data write operation, and to supply an internal address signal, which is generated by a counter circuit, to the second address bus line during a data erase operation.
Moreover, according to the present invention, in order to inform the outside that a certain core is busy as a data write or erase mode, each of the cores may be provided with a core block register for holding a data write or erase flag during a data write or erase operation when a data write or erase command for a block in each block is inputted, and there may be provided a core busy output circuit for monitoring the data write or erase flag of the core block register to output a core busy output serving as a data write or erase enable signal.
Moreover, the address line switching circuit may have therein a data polling signal generating circuit for a data polling signal informing the outside that a core is in a data write or erase mode when a data read demand is inputted to the core while the mode of the core is selected as the data write or erase mode.
In addition, according to the present invention, the first address bus line used for usual data read, the first data bus line and the first sense amplifier circuit connected to the first data bus line may be associated with each other for constituting a first data read path, and the second address bus line used for usual data write or erase, the second data bus line and the second sense amplifier circuit connected to the second data bus line may be associated with each other for constituting a second data read path, and the semiconductor device may have a high-speed data read mode, in which the operations of the first and second data read paths overlap with each other by a half period to carry out a high-speed data read.
In the high-speed read operation, the address buffer may comprise: a clock generating circuit for detecting a transition in inputted address to generate a clock; and first and second latches for alternately latching an inputted address in synchronism with the clock generated by the clock generating circuit, to transfer the inputted to address to the first and second address bus lines.
According to the present invention, (a) a dummy load capacity connected to the second power supply line used for data write or erase in accordance with the number of selected cores may be added, or (b) the driving capability of the data writing or erasing power supply connected to the second power supply line may be switched in accordance with the number of selected cores. Thus, it is possible to fix a transition in power supply regardless of the number of selected cores.
In addition, according to the present invention, the power supply switching circuit is preferably switched and controlled while causing a power supply transition so that the first and second power supply lines have the same potential. Thus, it is possible to prevent useless fluctuation in power supply due to the switching of the power supply.
Moreover, according to the present invention, each of the plurality of cores preferably has a plurality of blocks which are arranged in column directions by one or two columns and in row directions. Thus, it is possible to provide a closest layout of cores.
In this case, the first and second address bus lines and the first and second data bus lines may be arranged in row directions in parallel to the arrangement of the cores.
According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a power supply control circuit for detecting an internal power supply voltage to hold a transition in the internal power supply voltage at a set level, the power supply control circuit having a dummy load capacity (C) selectively connected in accordance with a load capacity of an internal power supply. The power supply control circuit may detect an external power supply voltage to generate a detection signal and change the dummy load capacity, which is to be connected, on the basis of the detection signal.
According to a further aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a power supply control circuit for detecting an internal power supply voltage to hold a transition in the internal power supply voltage at a set level, the power supply control circuit having a circuit for changing an internal power supply driving capability in accordance with a load capacity of an internal power supply. The power supply control circuit may detect an external power supply voltage to generate a detection signal and change the internal power supply driving capability on the basis of the detection signal.
According to a still further aspect of the present invention, a semiconductor device comprises: a plurality of functional blocks, each of which is arranged as a certain lump of circuit functions; a signal line, arranged in a region of each of the functional blocks, for exchanging a signal between each of the functional blocks and the outside; and a common bus line which is provided on a region of the plurality of functional blocks and commonly for the plurality of blocks and which is connected to the signal line via a contact.
According to the present invention, the plurality of functional blocks may be a core serving as a lump of memory cell circuits of the same kind, or each of the functional blocks may have different circuit functions, respectively. In either case, by providing a common bus line, which is utilized commonly for each the functional blocks, on a region of the functional blocks as an upper wiring of signal lines in each of the functional blocks, it is possible to greatly reduce the chip size in comparison with the case where a common bus line region is provided outside of the region of the functional blocks.
In addition, when each of the functional blocks is, e.g., a plurality of cores comprising a set of memory cells of the same kind, there may be provided a decoder circuit including a predecoder, attached to each of the cores, for decoding an address signal to select a core from the cores, and a row decoder and a column decoder for further decoding an output decode signal of the pre-decoder to select a matrix of each of the cores, and the common bus line may be provided over a region of the pre-decoder of each of the cores arranged in row directions.